There exist applications in which there is a need to generate a single internal clock, or multiple internal clocks, synchronized to a single input clock. The present invention fulfills that need.
Synchronous systems, such as synchronous computing systems, are widely used. In synchronous systems, different components are maintained in a desired phase relationship by an appropriate means. For example, in a synchronous computer, each event, or the performance of each operation, starts as a result of a signal generated by a clock. Provision of such a clock signal to many components may be difficult, especially as the size, complexity or operating frequency of the system increase. For example, integrated circuit components have been interconnected to form complex digital logic systems.
U.S. Pat. No. 4,059,842, issued Nov. 22, 1977 to Meacham, relates to a method and apparatus intended to cause at least approximate phase synchronization to be established between a timing sequence provided by a digital divider chain and a low frequency reference pulse train. A master oscillator apparently drives a digital divider chain (also known as a divide-by-N counter), which apparently constitute a source of timing sequences. The digital divider chain is composed of multiple divide-by-two stages rippled together. A low frequency reference pulse train source and an all-digital phase synchronizer apparently function to bring the timing sequence output of the divider chain into phase synchronism with the output of the source. The synchronizer is a logic circuit intended for resetting the digital divider chain to zero in every cycle of the divider's operation. The reset signal from the synchronizer is apparently generated by a first flip-flop which is reset to its "low" state during presence of a low state reference pulse, and which has the master oscillator pulse train applied to its toggle input. This apparently causes initiation of a reset pulse with either the coincidence of a positive-going transition of the low frequency reference pulse and a negative-going transition of the master oscillator pulse, or if they do not coincide, upon sequential occurrence of a positive-going transition of the low frequency pulse and the next negative-going transition of the master oscillator pulse. A second flip-flop is intended to be suitably connected to control the first flip-flop to prevent further changes to a "high" state until appearance of the next "low" state of the low frequency pulse which holds the first flip-flop at its "low" state. In other words, the two flip-flops are intended to be suitably connected to cause the first flip-flop to change to a "high" state in response to a master oscillator pulse at a predetermined portion of the low frequency reference pulse cycle. Any other changing to a "high" state of the first flip-flop is described as being prevented by a combination of presence of the "low" state of the low frequency pulse train and a latching effect produced by suitable connection of the second flip-flop. The all-digital phase synchronizer is described as being used to generate a reset pulse to the digital divider chain.
The low frequency reference signal of Meacham is described as continuous and related to the master oscillator output by the divisor of the digital divider chain. Thus, temporary loss of the low frequency reference signal could cause an erroneous result in the Meacham system. Also, Meacham provides no means to prevent noise from accidentally falsely triggering the reset circuit of the synchronizer. Meacham furthermore provides no means to indicate an oscillator tolerance fault, and from the use of the low frequency reference signal is apparently used to reset at low frequencies. This last limitation also imposes a limit on the accuracy of the phase synchronizer. With a sufficiently high oscillator clock frequency, the delay in ripple stages of the divider chain would be longer than the clock period, causing a complete failure of the Meacham apparatus.
U.S. Pat. No. 5,160,894, issued Nov. 3, 1992 to Westwick, appears to disclose a frequency synthesizer circuit having a counter, a latch/decoder, a programmable divider, and a wave shaper which together synthesize an output clock signal X. System clock signals M and N are each apparently provided to the counter and to the divider; clock signal M is also apparently provided to the latch/decoder. The counter apparently counts the number of system clock signal N periods that occur within one system clock signal M period; this count is apparently stored as a count value. The stored count value is apparently latched or decoded by the latch/decoder to produce a divisor which is apparently output from the latch/decoder to the divider. The divider apparently divides the clock signal N frequency by this divisor to provide what is described as a spiked waveform to the wave shaper. The wave shaper apparently alters the frequency and the duty cycle of the spiked waveform to produce the output clock signal X.
However, Westwick can produce only a single clock output signal X; if additional clock output signals are needed, then an additional such system is needed for each additional clock output signal desired. Also, each such system would produce a single fixed clock frequency output; the system must be modified, or the value of clock signal N must be changed, in order to produce other clock output signals. Even then, each such system would still produce only one clock output signal at any one time. Also, a certain relationship between clock signal M and clock signal N is needed to obtain the particular desired characteristics of output clock signal X. Also, clock signals M and N must be continuously produced, in order for the output clock signal X to be continuously produced. Also, Westwick will fail to provide a correct frequency output if clock signal M varies because the system depends on the stability of clock signal M to correct variances in clock signal N. Furthermore, no indication of error is provided in the event of a system or clock signal M or N failure.